EPTC 2026 (Electronics Packaging Technology Conference) is an academic conference held in Singapore on 2026-12-01. The paper submission deadline is 2026-06-15. Acceptance notifications are sent on 2026-07-10.
The Organising Committee of EPTC2026 warmly welcome your interest in submitting your latest work for possible presentation at EPTC2026. Only new and unpublished works will be considered. Your abstract and paper will be peer-reviewed by the EPTC Technical Program Committee. Depending on the recommendations of the reviewers and the availability of oral presentation slots, your paper may be assigned for oral presentation, interactive poster presentation, or rejected. All accepted papers, both oral and interactive poster, will be published in the conference proceedings and in IEEE Xplore, provided they have been presented at the conference.
Papers on all aspects of electronics packaging are welcome. They will be distributed over the following 12 Tracks:
Track Topics
Advanced Packaging: Primary focus of this technical domain on packaging system, architecture and application driven topics. System-level architectures including chiplets, 2.5D/3D/3.5D integration, SiP, heterogeneous integration using interposers (Si, RDL, organic, SiC) and silicon bridge die; and application-driven package design (AI, HPC, automotive, HBM, RF systems), and system-level co-design. Large-format substrates processing, including panel warpage control, yield challenges, and process scalability. Advanced IC substrates, including embedded substrate solution, glass core substrate and glass interposer.
Assembly and Manufacturing: The primary focus of this technical area is process and manufacturing technologies for advanced packaging. Topics include pre-bond wafers preparation includes warpage control and mitigation , backgrinding, thin die handling dicing, plasma dicing, particle reduction process technologies and package assembly processes such as flip chip, wire bonding, thermal compression bonding (TCB), chip stacking, Chip-to-wafer (C2W) fusion/ hybrid bonding, Additional areas of interest include board-level assembly; heat sink and spreader attachment, multi-chip and multi-package integration (SiP, MCP); flexible and printed electronics assembly; assembly yield optimization; The scope further extends Built-in self-test (BIST), burn-in, system-level testing, and high-throughput testing methodologies, which are critical to enabling advanced heterogeneous integration.
Electrical Simulation & Characterization: Signal and power integrity, high-speed and RF electrical modeling, electromagnetic simulation, and high-bandwidth interface analysis. Advanced measurement techniques for package and system-level electrical performance, including mmWave, co-packaged optics (CPO), and high-speed data communication systems. Power delivery network (PDN) design and noise suppression for large AI systems.
Emerging Technologies: Next-generation packaging for flexible and bioelectronics, MEMS/NEMS, and wide bandgap (SiC, GaN) devices; quantum device packaging including cryogenic integration, low-loss interconnects, qubit scaling, and integration with classical control electronics; and emerging concepts such as neuromorphic and in-memory computing and novel device–package–system co-integration architectures.
Interconnection Technologies: Primary focus of this technical domain on interconnect scaling and associated design and implementation challenges that cover materials selection, new processes and equipment capabilities. 1st-level interconnects including wire bonding, flip-chip, TSV, Cu pillar, micro-bumps, thermo-compression bonding (TCB) hybrid bonding, microbump fine-pitch interconnect scaling, and advanced bumpless technologies such as C2W and W2W hybrid bonding, electrical interconnection techniques for high-density integration.
Materials and Processing: Substrates (organic core, glass core); build-up films; polymer dielectrics; embedded substrate, lead frames and PCB materials; underfills, encapsulants, and molding compounds; thermal interface materials; novel solder alloys and die-attach materials; wafer and panel-level bonding/debonding materials; conductive adhesives; materials for harsh environments and power device packaging applications; and materials for hybrid bonding and high-power thermal management.
Mechanical Simulation & Characterization: Thermo-mechanical stress analysis; fatigue and fracture modeling; moisture sensitivity and diffusion effects; drop, shock, and vibration reliability; process-induced deformation and warpage; and physics-based lifetime prediction models for large and complex packages.
Optoelectronics & Display Packaging: Packaging for optical interconnects, fiber coupling and co-packaged optics (CPO). Silicon photonics integration includes PIC packaging, advanced coupling and laser integration, emerging non-silicon photonics platforms (InP, GaAs, SiN, polymer) and heterogenous III-V integration. Integrated electro-optical co-design, thermal and power management supporting applications such as micro/mini LED, AR/VR displays, and high-density optoelectronic modules.
Quality, Reliability & Failure Analysis: Reliability testing at device, package, and board levels, including accelerated life testing and qualification methodologies. Failure mechanisms such as interconnect fatigue, delamination, voiding, and hybrid bonding defects. Advanced diagnostics, inline monitoring, advanced metrology, defect inspection, and FA techniques including X-ray, acoustic, and optical methods.
Smart Manufacturing & Equipment Technology: AI/ML-driven manufacturing, smart factories, digital twins, and advanced process control (APC). Equipment innovations for electronic packaging spanning wafer-level, panel-level, and back-end assembly & test, for yield, reliability, and performance optimization. End-to-end data analytics for yield learning, process optimization, fault detection, and predictive maintenance across the entire semiconductor manufacturing value chain.
Thermal Management & Characterization: Heat dissipation strategies; thermal simulation and measurement; cooling technologies (air, liquid, microfluidic); thermal interface optimization; high-power device cooling; and system-level thermal design for high-power applications and data center.
Wafer-Level & Panel-Level Packaging: Wafer- and panel-level processes including fan-in/fan-out technologies, redistribution layers (RDL), micro-bumps, TSV and mega-pillars for high-density integration. High-precision pick-and-place, overlay metrology, distortion correction, and alignment control for fine-pitch integration. Test and inspection strategies across wafer-level and panel levels, including known good die (KGD) challenges for chiplet integration.
No comments yet.