Conference Information
PACT 2025: International Conference on Parallel Architectures and Compilation Techniques
https://pact2025.github.io/index
Submission Date:
2025-04-11
Notification Date:
2025-07-28
Conference Date:
2025-11-03
Location:
Irvine, California, USA
Years:
34
CCF: b   CORE: a   QUALIS: a2   Viewed: 28536   Tracked: 86   Attend: 7

Call For Papers
Scope

The International Conference on Parallel Architectures and Compilation Techniques (PACT) is a unique technical conference at the intersection of hardware and software, with a special emphasis on parallelism. PACT brings together researchers from computer architectures, compilers, execution environments, programming languages, and applications to present and discuss their latest research results, tools, and practical experiences.

PACT 2025 will be held as an in-person event in Irvine, California, USA. We encourage all authors of accepted papers to participate, and at least one author must attend the conference.

PACT seeks submissions in two categories:

    Research Papers
    Tools and Practical Experience (TPE) Papers

Topics of Interest

PACT welcomes submissions on topics including, but not limited to:

    Parallel architectures, including accelerators for AI and other domains
    Compilers and tools for parallel architectures
    Applications and experimental studies of parallel processing
    Computational models for concurrent execution
    Multicore, multithreaded, superscalar, and VLIW architectures
    Compiler and hardware support for reducing memory latencies
    Support for correctness in hardware and software
    Reconfigurable parallel computing
    Dynamic translation and optimization
    I/O issues in parallel computing and their application impact
    Parallel programming languages, algorithms, and applications
    Middleware and runtime system support for parallel computing
    Application-specific parallel systems
    Distributed computing architectures and systems
    Heterogeneous systems leveraging various accelerators
    In-core and in-chip accelerators and their optimization
    Applications of machine learning to parallel computing
    Large-scale data processing, including in-memory computing accelerators
    Insights from modern parallel applications for architecture and compiler design
Last updated by Dou Sun in 2025-03-09
Acceptance Ratio
YearSubmittedAcceptedAccepted(%)
20051193025.2%
20041222318.9%
20031442416.7%
20021192521%
20011262620.6%
20001072927.1%
19991143530.7%
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