Conference Information
ETS 2017 : European Test Symposium
Submission Date:
2016-12-13 Extended
Notification Date:
Conference Date:
Limassol, Cyprus
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Conference Location
Call For Papers
The IEEE European Test Symposium (ETS) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, applications, hot topics, and new trends in the area of electronic-based circuits and system testing and reliability. In 2017, ETS will take place at Amathus Beach Hotel, Limassol, Cyprus. It is organized by the University of Cyprus, which co-sponsors the event jointly with the IEEE Council on Electronic Design Automation (CEDA). 

ETS traditionally enjoys a strong balance among academic and industrial participants. In addition to regular Scientific Papers, Special Sessions, Panels, and Embedded Tutorials, ETS features Vendor Sessions and Table-Top Demos, a special track on Emerging Test Strategies (ETS2) where new issues are presented by the industry and are discussed in an informal atmosphere, as well as the new initiative of Industry Wish List where industry presents elevator talks on open issues that demand urgent solutions. ETS is the major event of the European Test Week that includes TSS (Test Spring School) and fringe workshops.

You are invited to participate and submit your contributions to ETS’17. The areas of interest include (but are not limited to) the following topics:

    Analog Test
    ATE Hardware and Software
    Automatic Test Generation
    Board Test and Diagnosis
    Boundary Scan Test
    Built-In Self-Test (BIST)
    Current-Based Test
    Defect-Based Test
    Delay and Performance Test
    Dependability and Functional Safety
    Design for Test (DfT)
    Design for Manufacturing (DfM)
    Diagnosis and Silicon Debug
    Economics of Test
    Emerging Technologies
    Failure Analysis

    Fault Modeling and Simulation
    Fault Tolerance
    GPU Test
    High-Speed I/O Test
    Low-Power IC Test
    Memory Test and Repair
    MEMS Test
    Microprocessor Test
    Mixed-Signal Test
    Multi-/Many-core Processor Test
    Nanotechnology Test
    On-line Test
    Power Issues in Test
    Reconfigurable System Test
    RF Test

    Security and Trust Issues in Test
    Sensor Test
    Signal Integrity Test
    SiP, Stacked, 3D IC Test
    SoC Test
    Soft Errors
    Standards in Test
    Statistical Learning in Test
    Test Compression
    Test Quality
    Test Synthesis
    Thermal Issues in Test
    Validation and Verification 
    Variability Issues in Test
    Yield Analysis and Enhancement 

Guidelines for Authors

Prospective authors are invited to submit novel, unpublished, and complete research contributions. Each submitted scientific paper should be a complete PDF manuscript, up to six (6) pages (inclusive of all figures, tables, and bibliography) in a standard IEEE format: A4 pages, two columns, single spaced, 10 points Times New Roman font. The IEEE template can be found here. Papers not compliant with the IEEE template or exceeding the page limit will be returned without review!

ETS fully complies with the IEEE publication policies regarding double submissions, plagiarism, etc. Authors unfamiliar with the IEEE official rules regarding double submissions and IEEE ethics are advised to read the Publication Guidelines section of the IEEE PSPB Operations Manual found here.

A submission of a scientific paper is considered a commitment that, upon acceptance, authors will submit their camera-ready version for inclusion in the formal proceedings and will present the paper (or the poster) at the symposium. Each accepted contribution must have at least one full paid registration by the time the camera ready paper is submitted for inclusion in the proceedings. ETS reserves the right to remove from IEEE Xplore papers and posters not presented at the symposium.
Last updated by Dou Sun in 2016-12-10
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