Conference Information
FPGA 2017 : International Symposium on Field-Programmable Gate Arrays
http://isfpga.org/
Submission Date:
2016-09-18
Notification Date:
2016-11-15
Conference Date:
2017-02-22
Location:
Monterey, California, USA
Years:
25
CCF: b   QUALIS: a2   Viewed: 7699   Tracked: 16   Attend: 0

Conference Location
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Call For Papers
1. Research Papers

We solicit research papers related to the following areas:

    FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
    FPGA Circuit Design: Circuits and layout techniques for design of FPGAs. Impact of future process and design technologies on FPGAs. Methods for analyzing and improving static and dynamic power, power and clock distribution, yield, manufacturability, security, reliability, and testability. Use of novel memory or nano-scale devices in FPGAs.
    CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power. High-level abstractions and tools for FPGAs: general-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Examples include hardware/software co-design, high-level synthesis, digital signal processing, compute acceleration, networking, and embedded systems.
    FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable computing, adaptive computing, and rapid-prototyping.
    Applications and Design Studies: Implementation of novel designs on FPGAs to achieve high-performance, low-power, security or high-reliability, making use of the unique flexibility provided by FPGA architectures. Application-domain studies to analyze or improve FPGA architectures.

Research submissions may be either:

Full: at most 10 pages, for a full presentation at the conference; or Short: at most 6 pages, for a brief presentation. The presentation time allocated to each submission will be determined by the Program Committee.

2. The Potential Roles for FPGAs in Deep Learning

Deep learning has garnered significant visibility recently as an Artificial Intelligence (AI) paradigm, with success in wide ranging applications such as image and speech recognition, natural language understanding, self-driving cars, and game playing (e.g., Alpha Go). The conference will devote a Wednesday pre-conference workshop towards the potential role of FPGAs in this important and fast-evolving domain.

We are therefore seeking submissions on topic areas such as (but not limited to): tutorial papers on deep learning highlighting future challenges and the potential role of programmable hardware in addressing them, research/design papers detailing FPGA implementations of deep learning training/inference accelerators, unique applications of reconfigurability in deep learning context, domain-specific programmable hardware architectures for deep learning, the potential uses for deep learning techniques within FPGA CAD software (e.g., for prediction and estimation).

Submissions should be at least 4 and at most 10 pages. Accepted submissions will be published in the proceedings and allocated a presentation time of up to one hour, appropriate to the content.

3. Panel Discussion Proposals

We also solicit proposals for the panel discussion at the conference banquet. The submission should outline the topic, questions to be addressed, and suggested speakers.

Submission Process

Submissions of all types should be made in the form of an English language PDF file, on-line at http://www.isfpga.org. Papers should use one of the ACM format templates posted at https://www.acm.org/publications/proceedings-template. Submissions must be received by September 18, 2016 at 11:59 PM (in any time zone).

Submissions will be considered for acceptance as full or short regular papers, workshop papers, or posters. Regular submissions related to the workshop topic may be scheduled for presentation during the workshop. Regular or workshop submissions will also be considered for acceptance as a poster. NOTE: Unlike previous years of the conference, full-length regular submissions will not be considered for acceptance as short papers.

The FPGA Symposium uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. Exceptions may be allowed, with prior approval of the Program Chair, in cases where the authors’ identity is vital to evaluating the paper (e.g., papers presenting updates of infrastructure used by the FPGA community). References to the authors’ prior work should be made in the 3rd person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as "Removed for blind review", but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission.
Last updated by Dou Sun in 2016-07-31
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